1. Field of the Invention
The present invention relates to a substrate voltage generation circuit, and in particular, to an input/output voltage detection type substrate voltage generation circuit.
2. Background of the Related Art
FIG. 1 illustrates a block diagram of a related art substrate voltage generation circuit. As shown in FIG. 1, the related art substrate voltage generation circuit includes a substrate voltage sensor 10 for detecting a voltage from a substrate 40. An oscillator 20 is driven by an output of the substrate voltage sensor 10 and an external row address strobe RASB signal. A charge pump 30 is for pumping an electric charge in accordance with an output from the oscillator 20 and delivering the electric charge to the substrate 40.
FIG. 2 illustrates a schematic circuit diagram of the related art substrate voltage generation circuit. As shown in FIG. 2, the substrate voltage sensor 10 includes a PMOS transistor 11 and NMOS transistors 12 and 13, which are connected in series between a power supply voltage VCC and a substrate voltage VBB, and an inverter 14. The inverter 14 inverts the output from a common connecting node "a" between the drains of the PMOS transistor 11 and the NMOS transistor 12. The source and body regions of PMOS transistor 11 are commonly connected, as are the gate and drain of NMOS transistor 13. The gates of the PMOS transistor 11 and the NMOS transistor 12 are commonly connected to ground voltage VSS.
The oscillator 20 includes a NAND-gate 21 for NANDing the externally applied RASB signal and the output from the inverter 14 of the substrate voltage sensor 10. NAND-gates 22, 23 and 24 are coupled in cascade series with each other and each receives the output from the NAND-gate 21 as one input. Series inverters 25 and 26 sequentially invert the output from the NAND-gate 24. The output of the NAND-gate 24 is also fed back and into the other input of the NAND-gate 22.
The charge pump 30 includes a pumping PMOS transistor capacitor 31 having its body connected to VCC and having its source and drain commonly coupled to the output of inverter 26 in the oscillator 20 at a node "b". The pumping PMOS transistor capacitor 31 pumps to VCC or -VCC in accordance with a clock signal from the inverter 26 in the oscillator 20. An NMOS transistor 32 is for discharging the output from the gate of the PMOS transistor pumping capacitor 31 to a VSS node and operates as a diode. An NMOS transistor 33 transmits the pumped electric charge to a substrate voltage VBB node.
The operation of the related art substrate voltage generation circuit will now be described. First, the electric potential at the output node "a" of the substrate voltage sensor 10 is determined in accordance with the variation in the voltage VBB of the substrate as follows.
When VSS&gt;VBB+2Vtn, the NMOS transistors 12 and 13 are turned on. In this case, VBB denotes the substrate voltage, and Vtn denotes a threshold voltage of an NMOS transistor. When enabled, the NMOS transistors 12 and 13 pass a current I1 so that the electrical potential at the output node "a" drops down below the logic threshold point of the inverter 14, and the output from the inverter 14 becomes high level. When VSS&lt;VBB+2Vtn, the electric potential at the output node "a" is pulled up to VCC. Thus, the output from the inverter 14 becomes low level.
As shown in FIG. 3C, when the voltage VBB at the substrate is 0 V, the electrical potential at the output node "a" is pulled up to VCC as shown in FIG. 3B, and the output from the inverter 14 becomes low level. Therefore, the oscillator 20 is operated when a low level RASB signal is externally inputted or when a low level signal is outputted from the substrate voltage sensor 10 (i.e., the substrate voltage VBB increases). Therefore, the oscillator 20 outputs a pulse signal "b" having a predetermined period as shown in FIG. 3A.
The charge pump 30 pumps an electric charge in accordance with the clock signal from the node "b" in the oscillator 20. The charge pump 30 outputs the pumped electrical charge to the substrate voltage VBB node to drop the increased substrate voltage VBB.
Namely, when a VCC level clock signal is inputted from the node "b", the pumping capacitor 31 of the charge pump 30 pumps the electric potential at a node "c" up to the level of VCC. At this time, since the drain and gate of the NMOS transistor 32 are coupled to each other, the NMOS transistor 32 is turned on in accordance with the pumped voltage VCC. Therefore, the electric potential at the node "c" pumped up to VCC is discharged to the VSS node until the electric potential of the node "c" reaches the threshold voltage Vt1 of the NMOS transistor 32.
When the clock signal from the node "b" in the oscillator 20 is low level, the pumping capacitor 31 pumps the electric potential at the node "c" to -VCC. At first, the electric potential at the node "c" drops by -VCC+Vt1 (the threshold voltage Vt1 at the NMOS transistor 32) and is increased up to a threshold voltage Vt2 at the NMOS transistor 33, thus becoming -Vt2. At this time, the voltage VBB at the substrate is 0 V.
The charge pump 30 repeatedly performs a pumping operation in accordance with the clock signal from the oscillator 20. When the electric potential at the node "c" becomes -VCC+Vt1+Vt2, VSS&gt;VBB+Vt1+Vt2 is obtained, and the NMOS transistors 12 and 13 are turned on. The oscillator 20 is not operated by a high level signal from the substrate voltage sensor 10, and the pumping operation is stopped.
FIG. 4 illustrates a related art data input/output terminal. The related art data input/output terminal includes NAND-gates 34 and 35. One input of NAND-gates 34 and 35 receives an enable signal EN, and the other inputs respectively receive output data DO and DOB. Inverters 36 and 37, respectively, invert the outputs from the NAND-gates 34 and 35. NMOS transistors 38 and 39 are coupled in series between the supply voltage VCC and the ground voltage VSS. The gates of the NMOS transistors 38 and 39 receive the outputs from the inverters 36 and 37, respectively. The body regions of the NMOS transistors 38 and 39 are coupled with the substrate voltage VBB.
When a low level voltage inputted into the data input/output terminal is reduced below -Vtn due to noise, etc., in a data write mode, the NMOS transistor 38 is turned on. Thus, a current Ids flows from VCC to the input/output terminal I/O. Therefore, a substrate current Isub is generated. The substrate current Isub is supplied to the substrate through the body region junction portion due to the current Ids, thus increasing the substrate voltage.
However, the related art substrate voltage generation circuit, operates in accordance with the substrate voltage sensing signal or the externally applied RASB signal. Then, an electric charge is supplied to the substrate. At this time, when increasing the driving capability of the substrate voltage generation circuit based on the current Isub at the data input/output terminal, the driving capability may be over-increased in the normal operation region, and the current consumption may be increased. In addition, the substrate voltage generation circuit is not stable with respect to a variation in the substrate voltage based on the current variation at the data input/output terminal.